(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of forming an improved etch stop layer for metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a common application for integrated circuit fabrication, a contact/via opening is etched through an insulating layer to an underlying conductive area to which electrical contact is to be made. A conducting layer material is deposited within the contact/via opening. The damascene and dual damascene processes have become a future trend in metallization. Trenches or vias and trenches are etched in an insulating layer. The trenches or vias and trenches are inlaid with metal to complete the contacts. In all of these processes, etch stop layers are required to accurately form the trenches and vias. A silicon carbide etching stop layer has a good copper diffusion barrier capability and a lower dielectric constant than silicon nitride. Nevertheless, moisture resistance of the silicon carbide is worse than that of silicon nitride. Also, low dielectric constant (k) material to silicon carbide etching selectivity needs to be improved.
U.S. Pat. Nos. 6,127,262 and 6,209,484 both to Huang et al shows an etching stop and anti-reflective coating film comprising silicon oxynitride deposited using a PECVD process. U.S. Pat. No. 5,585,304 to Hayashi et al teaches a silicon carbide or silicon nitride etching stop in a transparent layer process.
A principal object of the present invention is to provide an effective and very manufacturable method of forming a composite etching stop layer in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method of forming a composite etching stop layer wherein the top TEOS oxide layer prevents moisture attack to the bottom layer.
A further object of the invention is to provide a method of forming a composite etching stop layer having an improved selectivity of a low-k material to the composite etching stop material.
Yet another object of the invention is to provide a method of forming a composite etching stop layer having a lowered dielectric constant.
A still further object of the invention is to provide a method of forming a composite etching stop layer comprising a bottom etching stop layer and a top TEOS oxide layer.
In accordance with the objects of this invention a new method of forming a composite etching stop layer is achieved. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer to complete the composite etching stop layer.
Also in accordance with the objects of the invention, a method for fabricating an integrated circuit device using a novel composite etching stop layer is achieved. A composite etching stop layer is deposited overlying a substrate. An etching stop layer selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOCN, SiOC, and bis-benzocyclobutene (p-BCB) is deposited over the substrate. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer to complete the composite etching stop layer. A dielectric layer is deposited overlying the composite etching stop layer. An opening is etched through the dielectric layer stopping at the composite etching stop layer. The composite etching stop layer within the opening is removed. The opening is filled with a conducting layer to complete fabrication of the integrated circuit device.